[Research]     [Teaching]     [Misc]

Research Areas

• VLSI CAD and Design
  
• Physical Design Automation
• Reconfigurable Computing
• High Level Synthesis

Publications

1. Hao Li, Jian Huang, Philip Sweany, and Dijiang Huang, “FPGA Implementations of Elliptic Curve Cryptography and Tate Pairing
   over a Binary Field”, accepted by Journal of Systems Architecture (published by Elsevier), available online at here.
   
   
2. Jian Huang, Jooheung Lee, and Hao Li, “ A Fast FPGA Implementation of Tate Pairing in Cryptography
   over Binary Field”, to appear in International Conference on Security and Management, July 2008.
   
   
3. Hao Li and Yue Zhuo, “Criticality History Guided FPGA Placement Algorithm for Timing Optimization”,
   in Proceedings of GLSVLSI 2008, pp. 267-272, May 2008
   
   
4. Jian Huang, Hao Li, and Philip Sweany “An FPGA Implementation of Elliptic Curve Cryptography for Future Secure Web Transaction”,
   in International Conference on Parallel and Distributed Computing Systems (PDCS 2007), pp. 296-301, September 2007.


5. Jian Huang and Hao Li, “A Parallel Architecture for Motion Estimation and DCT Computation in MPEG-2 Encoder”,
   in Lecture Notes in Computer Science (ICA3PP-07) , Vol.4494, pp. 210-221, Springer-Verlag, June 2007.
   
   
6. Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, and Xianlong Hong, “New Timing and Routability Driven Placement
   Algorithms for FPGA Synthesis”, in Proceedings of GLSVLSI 2007, pp. 570-575, March 2007.


7. Yue Zhuo and Hao Li, “A Novel Timing and Congestion Driven Algorithm for FPGA Placement”,
   in Proceedings International Symposium on Field-Programmable Gate Arrays, pp. 224, February 2007.


8. Yue Zhuo, Hao Li, and Saraju Mohanty, “A Congestion Driven Placement Algorithm for FPGA Synthesis”,
   in Proceedings of International Conference on Field Programmable Logic and Applications, pp. 683-686, August 2006.


9. Hao Li, Srinivas Katkoori, and Zhipeng Liu, “Feedback Driven High Level Synthesis for Performance Optimization”,
   in Proceedings of 6th International Conference on ASIC, pp. 882-885, October 2005.


10. Wai-Kei Mak, and Hao Li, “Modern FPGA Placement”,
    in Proceedings of Emerging Information Technology Conference, August 2005, Taiwan.


11. S. Mohanty, R. Velagapudi, V. Mukherjee, and Hao Li, “Reduction of Direct Tunneling Power Dissipation
    during Behavioral Synthesis of Nanometer CMOS Circuits”, in Proceedings of ISVLSI 2005, pp.248-249, May 2005.


12. Hao Li, Wai-Kei Mak, and Srinivas Katkoori, “Power Minimization Algorithms for LUT Based FPGA Technology Mapping”,
    ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol.9, No.1, pp. 33-51, January 2004.


13. Hao Li, Srinivas Katkoori, and Wai-Kei Mak, “Force-directed Performance Driven Placement Algorithm for FPGAs”,
    in Proceedings of ISVLSI 2004, pp.193-198, Feburary 2004.


14. Hao Li, Wai-Kei Mak, and Srinivas Katkoori, “An Efficient LUT-Based FPGA Technology Mapping Algorithm for Power Minimization&rdquo,
    in Proceedings of ASP-DAC, pp.353-358, January 2003. (Nominated for Best Paper Award)


15. Hao Li, Wai-Kei Mak, and Srinivas Katkoori, “LUT-based FPGA Technology Mapping for Power Minimization with Optimal Depth”,
    in Proceedings IEEE WVLSI 2001 , pp.123-128, April 2001.

Students

Affiliations

IEEE

ACM

Experiences

• June 2000, Attended the 37th Design Automation Conference with Young Student Support.
• May - August, 2001, Internship at Mentor Graphics, San Jose, CA.
• Jan. 21-24, 2003 Attended the Asia and South Pacific Design Automation Conference as a speaker, Kitakyushu Japan.

Links

Ph.D. Advisor

Dr. Srinivas Katkoori at the University of South Florida.

Miscellaneous

Last updated 4/17/2008