Chapter 7
Memory Management

Simple Paging

Processes typically do not use their entire space in memory all the time. Paging

Divides the process image into fixed-sized pages,
Selectively allocates pages to frames in memory,
Manages pages in memory (moves, removes, and reallocates pages).

The 90/10 Rule: Processes spend 90% of their time accessing 10% of their space in memory.

Implication: We want to keep only those parts of a process in memory that are actually being used.

Features of paging:

Pages greatly simplify the hole-fitting problem.
The logical memory of the process is contiguous, but the pages need not be allocated contiguously in physical memory.
Not all pages of the process image need be in memory at the same time.
By dividing memory into fixed-size pages, we can eliminate external fragmentation. (But we introduce what? And how much of it?)

Paging Hardware

How do we find physical addresses when pages are not allocated contiguously in memory?

Assumptions:

Processes use a logical address space consisting of contiguous memory locations with addresses starting at 0.
The O/S divides the process image into consecutive pages. The logical address identifies the page and page offset.
A page table keeps track of the page frame in memory in which a page is located.
Special paging hardware translates the logical addresses into physical addresses.

Figure 8.5 goes here.

Paging is a form of dynamic relocation, where each logical address is bound by the paging hardware to a physical address. (Think of the page table as a set of base/limit registers, one for each frame.)

Mapping is invisible to the process; the O/S maintains the mapping and the hardware does the translation.

Protection is provided with the same mechanisms that were used in dynamic relocation.

Some details:

Page size is typically a power of 2 between 512 and 8192 bytes per page.
Assuming a page size of 2^n and a logical address space of size 2^m, then
- The high order m-n bits of the logical address select the page;
- The low order n bits select the offset in the page.

Example 1

        virtual        page
	memory         table           frames in memory
         _____          ___            _____      _____
        |     |        |   |          |     |    |     |
      P0|     |       0| 2 |        F0|     |  F8|     |
        |_____|        |___|          |_____|    |_____|
        |     |        |   |          |     |    |     |
      P1|     |       1| 6 |        F1|     |  F9|     |
        |_____|        |___|          |_____|    |_____|
        |     |        |   |          |     |    |     |
      P2|     |       2|11 |        F2|     | F10|     |
        |_____|        |___|          |_____|    |_____|
        |     |        |   |          |     |    |     |
      P3|     |       3| 9 |        F3|     | F11|     |
        |_____|        |___|          |_____|    |_____|
                                      |     |    |     |
                                    F4|     | F12|     |
                                      |_____|    |_____|
         memory size = 256 bytes      |     |    |     |
         page size   = 16 bytes     F5|     | F13|     |
                                      |_____|    |_____|
                                      |     |    |     |
                                    F6|     | F14|     |
                                      |_____|    |_____|
                                      |     |    |     |
                                    F7|     | F15|     |
                                      |_____|    |_____|

1. Question: How many bits for an address, assuming that we can address each byte?

Answer: 8

2. Question: What part of the address is p? What part is d?

Answer: p is the leftmost 4 bits; d is the leftmost 4 bits.

3. Question: Given logical address 24, do the logical to physical address translation.

Answer: Logical address 24 is address 00011000; so p = 0001, d = 1000. Therefore, this location is logical page 1, offset 8. The page table shows that logical page 1 is in main memory in page frame 6. Therefore, the physical address is 01101000, or 104.

Example 2

        virtual        page
	memory         table           frames in memory
         _____          ___            _____      _____
        |     |        |   |          |     |    |     |
      P0|     |       0| 2 |        F0|     |  F8|     |
        |_____|        |___|          |_____|    |_____|
        |     |        |   |          |     |    |     |
      P1|     |       1| 6 |        F1|     |  F9|     |
        |_____|        |___|          |_____|    |_____|
        |     |        |   |          |     |    |     |
      P2|     |       2|11 |        F2|     | F10|     |
        |_____|        |___|          |_____|    |_____|
        |     |        |   |          |     |    |     |
      P3|     |       3| 9 |        F3|     | F11|     |
        |_____|        |___|          |_____|    |_____|
                                      |     |    |     |
                                    F4|     | F12|     |
                                      |_____|    |_____|
         memory size = 256 bytes      |     |    |     |
         page size   = 16 bytes     F5|     | F13|     |
                                      |_____|    |_____|
                                      |     |    |     |
                                    F6|     | F14|     |
                                      |_____|    |_____|
                                      |     |    |     |
                                    F7|     | F15|     |
                                      |_____|    |_____|

1. Question: How many bits for an address, assuming that we can address only 4-byte words?

Answer: Since there are 4 words per page, we only need 2 bits to represent the offset. We still need 4 bits to represent the page number, so we need 6 bits for an address.

2. Question: What part of the address is p? What part is d?

Answer: p is the leftmost 4 bits; d is the rightmost 2 bits.

3. Question: Given logical address 13, do the logical to physical address translation.

Answer: Logical address 13 is address 001101; so p = 0011, d = 01. Therefore, this location is logical page 3, offset 1. The page table shows that logical page 3 is in main memory in page frame 9. Therefore, the physical address is 100101, or 37.

Making Paging Fast

How should we store the page table?

Memory. Too slow.
Registers. Too expensive.
Translation Lookaside Buffer (TLB). Just right.

A TLB is a fast fully associative memory that stores page numbers (the key) and the frames (the value) in which they are stored. Since, if memory accesses exhibit locality then address translation also exhibits locality, we are usually using only a small fraction of all pages at any time. Hence if we have those page table entries in some fast memory, we almost get the effect of having the whole page table in fast memory.

Typical TLB sizes range from 8 to 2048 entries.

Figure 8.10 goes here.

In addition to what is shown in the diagram, the TLB also needs to have a valid bit v for each entry that shows whether or not that entry is up-to-date.

Paging and the TLB:

A typical sequence of events with paging and a TLB:

Process needing k pages arrives.
If k page frames are free, the O/S allocates all k pages to the free frames. Otherwise, we need a page replacement algorithm.
The O/S puts the first page in a frame and enters the frame number as the first entry in the page table. It then puts the second page in a frame...
O/S marks all TLB entries as invalid.
O/S starts process.
As process executes, O/S loads TLB entries as each page is accessed, using some page replacement algorithm when the TLB is full.

On a context switch:

Flush the TLB.
Option: Store the TLB in the PCB and reload it later.

Relative Costs of Paging with a TLB

Question: What is the effective memory access cost if the page table is in memory, there is no TLB, and all needed pages are in main memory?

Answer: One memory cycle is needed to access the page table, and then another memory cycle to fetch the data. Hence, if t is the time for one memory cycle, the effective memory access time is 2t.

Question: What is the effective memory access cost with a TLB, assuming a 95% TLB hit rate?

Answer: If the page to be accessed has an entry in the TLB, then only one memory cycle is needed to fetch data; otherwise, 2 memory cycles are needed. Thus the effective memory access time is .95(t) + .05(2t) = 1.05t.

Chapter 7 Memory Management

Simple Paging

Chapter 7
Memory Management