Mahadevan Gomathisankaran

Testing Framework

New security architectures are difficult to prototype and test. They require interactions between hardware, operating systems, and applications, making them hard to simulate and monitor. In this project we are designing and prototyping a testing framework using a virtualization platform which emulates the behavior of new hardware security architecture in the virtual CPU, and performs a wide range of hardware and software attacks on the system under test. Our testing framework significantly speeds up development of the testing environment and infrastructure, and provides APIs for launching attacks and monitoring the effects of an attack on the hardware and software layers, which is especially convenient during the design and validation phases for new hardware software architectural solutions.

[ Testing Framework ]

Secure Systems Architecture

My research in this area started with solving the fundamental problem of enabling the micro-architecture to provide tamper resistant isolated execution environments for protected applications (Arc3D). The threat model included Operating Systems, Hardware and Software based attacks. I also looked at the problem of verifying the integrity of the embedded systems device (TIVA). Currently I am looking at the problem using virtualization to develop a test-bed to test these micro-architectural solutions.

[ Arc3D | TIVA ]

Cryptography

Conventional block ciphers (DES,AES,Serpent) derive their security from an embedded secret, more commonly referred to as a key. One of the inputs, key, in each round is secret whereas the round functions themselves are public. The secret, however, is combined with the state in a limited way, as an xor, during each round. I am investigating a simple yet novel approach wherein the round functions themselves become the secret, while the function schema is a publicly published algorithm. The intuition is to use reconfigurable gates as round functions and define their configurations as the secret (or key). Hence the complexity of such a cryptographic function is derived from the fact that almost all of the round processing is driven by the secret (truth tables).

The main advantages of our design are:

• Key size much greater than the block length can be easily accommodated. This allows for higher security guarantees without having to increase the latency of cipher operation.
• Smaller block lengths are well-suited for processor level instruction encryption when the encryption system is placed in-line into a processor pipeline.
• Area and time efficient hardware implementation reduces the processing overhead drastically for security.
• Simplicity of the design.

[ REBEL | Maya | Tantra ]

Low Power VLSI

The increasing sub-threshold leakage current levels with newer technology nodes has been identified by ITRS as one of the major fundamental problems faced by the semiconductor industry. SRAM arrays which are used widely as a system component, such as caches and register files, in both high-performance and portable systems, are getting to be dominant power consumers because of their large capacity and area. Hence any reduction in cache energy can result in considerable overall power reduction. I proposed a novel circuit technique using depletion mode devices, to reduce the static energy of SRAM array in an on-chip cache by 90% without any performance impact.

[ Warm SRAM ]