Post Doctoral Research

Secure systems solution involve both hardware and software components. Conventional way of testing these solutions is to reason the strengths and weaknesses of the architecture and test these components independently. The correctness of such an approach is entirely dependent on the designer of those components. We are investigating a novel testing framework that allows testing of both hardware and software components together in a realistic execution environment. We are designing and developing such a framework using virtualization technology.

Graduate Research

Reconfigurable Block Encryption Logic:

Conventional block ciphers (DES,AES) derive their security from an embedded secret, more commonly referred to as a key. The secret, however, is combined with the state in a limited way, as an xor, during a round. The xor based mixing of the cipher state and the secret leads to some vulnerabilities based on linear and differential cryptanalysis. The complexity of extracting the secret or its properties is proportional to the non-linearity, among many other attributes, of the round functions. We proposed a simple yet novel approach wherein the round functions themselves become the secret, while the function schema is a publicly published algorithm. The intuition is to use reconfigurable gates as round functions and define their configurations as the secret (or key). Hence the complexity of such a cryptographic function is derived from the fact that almost all of the round processing is driven by the secret (truth tables).

Efficient solution to memory integrity verification problem:

Embedded devices are omnipresent and pervade all facets of human life. Their sheer numbers and wide presence make them amenable to tampering. A tampered sensor could misrepresent its environment or a tampered PDA could relay the private data of the user to a third party. Hence verification of these devices is a relevant problem. However, such verification needs to be extremely efficient and mostly automated given the sheer numbers of these devices. Moreover, the verification architecture will not be practical if it compromises the IP of the software running on these devices. We proposed a novel hardware architecture TIVA and a schema for such a verification mechanism which satisfies all the requirements of a verification system without compromising the IP of the system being verified.

Architecture support for 3D Obfuscation:

Software obfuscation is a key technology in IP-protection. However, software only solutions often do not have robustness of crypto methods. Complete control flow obfuscation methods such as Cloakware have the limitation that they cannot hide the correct control flow information from the prying eyes of the OS/end user. An additional weakness in these schemes is that observation of repeated dynamic execution often gives away the obfuscation secrets. We proposed a minimal architecture, Arc3D, to support efficient obfuscation of both static binary file system image and dynamic execution traces. This obfuscation covers three aspects: address sequences, contents, and second-order address sequences.

Leakage energy reduction in SRAM Arrays:

Static subthreshold leakage has emerged as one of the major impediments in CMOS scaling. Microprocessors attain significant performance improvement by increasing the size and associativity of on-chip caches. Both dynamic switching energy, and static subthreshold leakage current induced energy of on-chip caches are already significant factors in over-all power consumption of the processors. The static leakage energy would overwhelm the dynamic energy for these caches as the static energy grows exponentially with reduction in feature size. We presented a SRAM cell design in dep-warmup CMOS and its block level implementation. The detailed SPICE simulations estimate the static leakage energy savings for L1 caches at more than 90% without any affect on the performance.

Lab Coordinator

Teaching Assistant for two semesters for "Introduction to Micro-controllers" (CPRE211) course at Iowa State University. My responsibilities included coordinating the labs, setting up the exercises, and grading. I enjoyed the experience of interacting with students during these lab sessions. This was a real motivating factor for my choice of academic career.

Teaching Assistant

Assisted Dr. Akhilesh Tyagi with his "Advanced Computer Architecture" (CPRE681) graduate level course. I prepared and delivered lectures related to the recent research works in the area of Secure Computer Architectures.